Research

2025

1. A Quantization Strategy for Communication-Efficient DNN Inference in Vehicular Edge Computing

   2025

   Submitted to IEEE Embedded Systems Letters (ESL)

   Abs

   As Deep Neural Network (DNN) applications drive the development of intelligent connected vehicles (ICV), there is a clear need for efficient and reliable DNN processing in ICVs. Vehicular Edge Computing (VEC) is a promising paradigm to meet such demand, where vehicles can cooperate to perform computation tasks. However, there is currently a mismatch between vehicles’ communication capacities and computation capacities, making the communication channel a scarce resource for DNN inference workloads. This paper proposes a design-time deep reinforcement learning (DRL)-based quantization strategy to alleviate this issue under dynamic communication and computing environments in VEC while complying with a pre-defined accuracy drop constraint. Compared to greedy strategies, our results show significant improvements in communication traffic and inference latency.

2023

1. Design of Analog-AI Hardware Accelerators for Transformer-based Language Models (Invited)

   G. W. Burr, H. Tsai, W. Simon, I. Boybat, S. Ambrogio, C.-E. Ho, and 28 more authors

   In 2023 International Electron Devices Meeting (IEDM), 2023

   Abs DOI

   Analog Non-Volatile Memory-based accelerators offer high-throughput and energy-efficient Multiply-Accumulate operations for the large Fully-Connected layers that dominate Transformer-based Large Language Models. We describe architectural, wafer-scale testing, chip-demo, and hardware-aware training efforts towards such accelerators, and quantify the unique raw-throughput and latency benefits of Fully- (rather than Partially-)Weight-Stationary systems.